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Tag Archives: Cache

Zero cache miss – Really ?

Posted on 17 August, 2014 by Ran Lifshitz
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In the packet processing world, usually the goal is to achieve one cache miss throughout the “life of the packet” in the system. Not many know, but in the latest Intel architectures, there is a new feature called “DCA”, which stands for Direct Cache Access.
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Posted in Software development | Tagged Cache, Cache line, Cache miss | Leave a reply

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